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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD6432 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 gsm 3 v transceiver if subsystem functional block diagram saw bp op amp AD6432 pa rf synth if synth plo features fully compliant with standard and enhanced gsm specification dc-350 mhz rf bandwidths 80 db gain control range i/q modulation and demodulation onboard phase locked tunable oscillator on-chip noise roofing if filters ultralow power design 2.7 vC3.6 v operating voltage user-selectable power-down modes small 44-lead tqfp package interfaces directly with ad20msp410 and ad20msp415 gsm baseband chipsets applications i/q modulated digital wireless systems gsm mobile radios gsm pcmcia cards general description the AD6432 if ic provides the complete transmit and receive if signal processing, including i/q modulation and demodula- tion, necessary to implement a digital wireless transceiver such as a gsm handset. the AD6432 may also be used for other wireless tdma standards using i/q modulation. the AD6432s receive signal path is based on the proven archi- tecture of the ad607 and the ad6459. it consists of a mixer, gain-controlled amplifiers, integrated roofing filter and i/q demodulators based on a pll. the low noise, high-intercept variable-gain mixer is a doubly-balanced gilbert-cell type. it has a nominal C13 dbm input-referred 1 db compression point and a 0 dbm input-referred third-order intercept. the gain-control input accepts an external control voltage input from an external agc detector or a dac. it provides an 80 db gain range with 27.5 mv/db gain scaling, where the mixer and the if gains vary together. the i and q demodulators provide inphase and quadrature baseband outputs to interface with analog devices ad7015 and ad6421 (gsm, dcs1800, pcs1900) baseband convert- ers. an onboard quadrature vco, externally phase-locked to the if signal, drives the i and q demodulators. the quadrature phase-locked oscillator (qplo) requires no external compo- nents for frequency control or quadrature generation, and de- modulates signals at standard gsm system ifs of 13 mhz, or 26 mhz with a reference input frequency of 13 mhz; or, in general, 1x or 2x the reference frequency. maximum reference frequency is 25 mhz. this reference signal is normally provided by an external vctcxo under the control of the radios digital signal processor. the transmit path consists of an i/q modulator and buffer amplifier, suitable for carrier frequencies up to 300 mhz and provides an output power of C17.5 dbm in a 50 w system. the quadrature lo signals driving the i and q modulator are generated internally by dividing by two the frequency of the signal presented at the differential lo port of the AD6432. in both the transmit and receive paths, onboard filters provide 30 db of stopband attenuation. the AD6432 comes in a 44-lead plastic thin quad flatpack (tqfp) surface mount package.
C2C rev. 0 AD6432Cspecifications (t a = +25 8 c, v p = 3.0 v, gref = 1.25 v unless otherwise noted) parameter conditions min typ max units rx rf mixer rf input frequency 350 mhz agc conversion gain variation z in = 150 w : 0.2 v < v gain < 2.4 v C3 to +15 db input 1 db compression point at v gain = 2.4 v, z in = 150 w C13 dbm input third-order intercept at v gain = 0.2 v, rf in = C25 dbm 0 dbm ssb noise figure at z in = 150 w , f rf = 246 mhz, f lo = 272 mhz, v gain = 0.2 v 10 db rx if amplifier agc gain variation 0.2 v < v gain < 2.4 v C14 to 48 db input resistance at v gain = 0.2 v 5 k w operating frequency range 10 50 mhz gain control total gain control range mixer+if+demod, 0.2 v < v gain < 2.4 v 80 db control voltage range at gain 0.2 2.4 v gain scaling 27.5 mv/db gain law conformance 0.1 db bias current at gref C0.5 m a input resistance at gain 20 k w integrated if filter bpf center frequency f ref = 13 mhz ifs0 = 1 0 = connect to ground, 1 = connect to v p 13 mhz ifs0 = 0 0 = connect to ground, 1 = connect to v p 26 mhz bpf C3 db bw f ref = 13 mhz ifs0 = 1 0 = connect to ground, 1 = connect to v p 5 mhz ifs0 = 0 0 = connect to ground, 1 = connect to v p 10 mhz i and q demodulator demodulation gain 17 db output voltage range differential 0.3 v pos C 0.2 v output voltage common-mode level not power supply independent 1.5 v output offset voltage differential, v gain = gref C150 +150 mv error in quadrature differential from i to q, if = 13 mhz 1 3.5 degrees amplitude match 0.25 db i/q output bw c load = 10 pf 3 mhz output resistance each pin 4.7 k w quadrature if pll operating frequency range 10 50 mhz reference frequency voltage level 200 mv p-p reference frequency range 25 mhz acquisition time using 1 k w , 1 nf loop filter 80 m s transmit modulator carrier output frequency 300 mhz output power r load = 150 w , power at final 50 w , f if = 272 mhz C17.5 dbm input 1 db compression point r load = 150 w (differential) 14 dbm i/q input signal amplitude differential 2.056 v p-p i/q input signal required dc bias 1.2 v i/q input bw 1 mhz i/q input resistance 100 k w i/q phase balance with los 2nd harmonic 30 dbc bellow fundamental 1.5 degrees i/q amplitude balance with los 2nd harmonic 30 dbc bellow fundamental 0.1 db output harmonic content r load = 150 w C45 (3rd) dbc C65 (5th) dbc carrier feedthrough f carrier = 272 mhz C33 dbc sideband suppression i and q inputs driven in quadrature C37 dbc
C3C rev. 0 AD6432 parameter conditions min typ max units lo port (lolo and lohi) input frequency 200 600 mhz input signal voltage range differential 200 mv p-p input resistance input pull-up resistors to v pos (each pin) 500 w auxiliary op amplifier small signal C3 db bandwidth 50 mhz input signal voltage range 0.1 v pos C 2.1 v input offset voltage 4mv input bias current C150 na output signal voltage range with r load > 4 k w 0.1 v pos C 0.2 v power consumption supply voltage 2.7 3 3.6 v transmit mode 13 ma receive mode at v gain = 1.2 v 13 ma sleep mode < 5 m a operating temperature range C25 +85 c notes all reference to dbm is relative to 50 w . specifications subject to change without notice. absolute maximum ratings 1 supply voltage vpdv, vppx, vpdm, vpfl, vppc, vprx, to cmtx, cmrx, cmif, cmd . . . . . . . . . . . . . . +3.6 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . 600 mw operating temperature range . . . . . . . . . . . C25 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering (60 sec) . . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 44-lead tqfp package: q ja = 126 c. pin configuration 29 30 31 32 33 27 28 25 26 23 24 40 39 38 41 42 43 44 36 35 34 37 3 4 5 6 7 1 2 10 11 8 9 12 13 14 15 16 17 18 19 20 21 22 top view (pins down) vpdv modo gnd cmtx lolo lohi cmrx gnd rflo rfhi gnd fref gnd ifs0 cmdm fltr vpfl vpdm irxp irxn qrxp qrxn vptx itxp itxn qtxp qtxn txpu pcap pcam gnd vprx mxhi mxlo iflo ifhi vppc cmif cmif rxpu gain gref gnd pcao AD6432 ordering guide temperature package package model range description option* AD6432ast C25 c to +85 c 44-pin plastic st-44 tqfp *st = thin quad flatpack. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD6432 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD6432 C4C rev. 0 pin function descriptions pin label description function 1 gnd pcb ground not bonded to ic 2 modo tx modulator output ac coupled, drives 150 w into 50 w 3 vpdv lo2 divided by 2 supply voltage v pos 4 cmtx on-chip tx mixer common ground 5 lolo differential rx mixer lo2 input negative ac coupled, v pos to v pos C 100 mv 6 lohi differential rx mixer lo2 input positive ac coupled, v pos C 100 mv to v pos 7 cmrx on-chip rx mixer common ground 8 gnd pcb ground not bonded to ic 9 rflo differential rx mixer if1 input negative ac coupled 10 rfhi differential rx mixer if1 input positive ac coupled 11 gnd pcb ground not bonded to ic 12 vprx rx section supply voltage v pos 13 mxhi differential rx if1/if2 mixer output positive see figure 30 14 mxlo differential rx if1/if2 mixer output negative see figure 30 15 cmif on-chip rx if2 common ground 16 iflo differential rx if2 input negative ac coupled 17 ifhi differential rx if2 input positive ac coupled 18 cmif on-chip rx if2 common ground 19 rxpu rx enable (power-up) off = low < 0.6 v, on = high > 2.5 v 20 gain rx vga gain control input 0.2 vC2.4 v using 3 v supply. max gain at 0.2 v 21 gref rx vga reference voltage 1.2 v typ 22 gnd pcb ground not bonded to ic 23 qrxn differential demodulator q output negative internal 4.7 k w resistor in series with the output 24 qrxp differential demodulator q output positive internal 4.7 k w resistor in series with the output 25 irxn differential demodulator i output negative internal 4.7 k w resistor in series with the output 26 irxp differential demodulator i output positive internal 4.7 k w resistor in series with the output 27 vpdm demodulator supply voltage v pos 28 vpfl i/q lo pll filter cap. supply voltage to v pos with good decoupling 29 fltr i/q lo pll filter referenced to vpfl 30 cmdm on-chip demodulator common ground 31 ifs0 if2 frequency select bit 0 = low < 0.6 v, 1 = high > 2.5 v 32 gnd pcb ground not bonded to ic 33 fref reference input (13 mhz for gsm) ac coupled. use 200 mv p-p input signal 34 vppc auxiliary op amp supply voltage v pos 35 pcao auxiliary op amp output active when txpu is high 36 gnd pcb ground not bonded to ic 37 pcam differential auxiliary op amp input negative 0.1 v to v pos C 2.1 v 38 pcap differential auxiliary op amp input positive 0.1 v to v pos C 2.1 v 39 txpu tx enable (power-up) low < 0.6 v, high > 2.5 v 40 qtxn differential modulator q input negative dc coupled, 1.2 v 514 mv 41 qtxp differential modulator q input positive dc coupled, 1.2 v 514 mv 42 itxn differential modulator i input negative dc coupled, 1.2 v 514 mv 43 itxp differential modulator i input positive dc coupled, 1.2 v 514 mv 44 vptx tx section supply voltage v pos
AD6432 C5C rev. 0 12 13 14 15 16 17 18 19 20 21 22 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 top view (pins down) txpu r3 49.9 w c1 100pf r9 84 w modo r25 1k w c29 0.1 f r34 0 w c11 0.01 f c10 1000pf c32 0.1 f vs2 vpdv decoupling vs1 r2 0 w r23 123 w qtxn qtxp itxn pcap r30 49.9 w c5 0.01 f c9 0.1 f r11 1k w r12 0 w r1 1k w r14 249 w c18 0.1 f 1 2 3 r10 500 w r8 0 w ifs0 r32 49.9 w c36 1000pf r6 0 w c41 0.01 f c17 0.1 f c23 0.01 f r7 0 w c6 47pf c8 47pf irxp irxn qrxp qxrn c28 0.1 f vptx decoupling c14 0.01 f c15 100pf 4 6 lolo itxp t1 vs1 rfhi c2 100pf r31 0 w vs1 c30 0.1 f c3 0.01 f mxhi mxlo c43 0.047 f c44 0.047 f c4 0.047 f r4 49.9 w c7 0.047 f r5 49.9 w iflo ifhi rxpu gain gref c39 0.01 f c40 0.01 f ifs0 rxpu vs1 gnd c7 4.7 f gain gref txpu c7 4.7 f j1 j3 j4 j5 vs2 vs1 pcao fref vs1 vpdv modo gnd cmtx lolo lohi cmrx gnd rflo rfhi gnd fref gnd ifs0 cmdm fltr vpfl vpdm irxp irxn qrxp qrxn vptx itxp itxn qtxp qtxn txpu pcap pcam gnd vprx mxhi mxlo iflo ifhi vppc cmif cmif rxpu gain gref gnd pcao AD6432 vppc decoupling r39 open pcam figure 1. characterization board
AD6432 C6C rev. 0 3 1 2 txpu itx qtx modo loip rfhi mxout vs1 vs2 gnd vp vn gain ifin fref irx qrx pcap pcao 3 1 2 rxpu interface box to test instr r22 50 w 7 6 5 1 2 3 4 ad824 vp vn 14 13 12 11 10 9 8 r1 10k w r2 10k w r5 10k w vp c1 0.1? r8 20k w r6 20k w r7 10k w r3 20k w r4 20k w vdc qtx r21 50 w itx r9 25 w r10 10k w r11 10k w vn r12 25 w r13 10k w r14 10k w c2 1pf r15 10k w r20 25 w r16 10k w r19 25 w r18 10k w r17 10k w itxp itxn qtxp qtxn vdc 5 6 7 8 4 3 2 1 gm gm v p v n ad830 a=1 r31 20k w r30 20k w mxlo mxhi c8 0.1? vn c7 0.1? mxout vp r25 50 w 5 6 7 8 4 3 2 1 gm gm v p v n ad830 a=1 qrxn qrxp c5 0.1? vn c6 0.1? qrx vp r24 50 w 5 6 7 8 4 3 2 1 gm gm v p v n ad830 a=1 irxn irxp c4 0.1? vn c3 0.1? irx vp r23 50 w ifin r28 50 w c12 0.1? v n c10 0.1? v p 1 2 3 4 8 7 6 5 v p v n a=1 gm gm ad830 iflo r26 50 w r27 50 w c11 0.1? v n c9 0.1? v p 1 2 3 4 8 7 6 5 a=1 gm gm ad830 ifhi c13 0.1? 1 2 3 ad1580 nc v+ v r29 10k w vp vdc vgref notes: vp = +5v vn = ?v ifs0 vp itxp itxn qtxp qtxn modo loip rfhi mxhi mxlo iflo ifhi fref irxp irxn qrxp qrxn pcap pcao gnd txpu gain gref gnd vs2 ifs1 ifs0 rxpu vs1 j1 interface box to char board figure 2. characterization test set
AD6432 C7C rev. 0 rf frequency ?mhz single sideband rx mixer noise figure ?db 11 6 150 450 200 250 300 350 400 10.5 9 7.5 7 6.5 10 9.5 8.5 8 r in = 50 w , if = 13mhz r in = 50 w , if = 45mhz r in = 50 w , if = 26mhz r in = 400 w , if = 13mhz figure 3. rx mixer noise figure vs. rf frequency, t a = +25 c, v pos = 3 v, v gref = 1.2 v, v gain = 0.2 v frequency ?mhz 900 800 50 550 100 150 200 250 300 350 400 450 500 700 600 500 400 shunt resistance ? w 300 200 100 2.5 3.0 3.5 4.0 4.5 5.0 r s v gain = 2.4v r s v gain = 1.2v r s v gain = 0.2v c s v gain = 2.4v c s v gain = 1.2v c s v gain = 0.2v shunt capacitance ?pf figure 4. rx mixer input impedance vs. rf frequency, v pos = 3 v, t a = +25 c, v gref = 1.2 v rf frequency ?mhz 16 14 150 175 200 250 300 350 12 10 8 6 4 2 0 gain ?db ? ? ? 225 275 325 v gain = 0.2v v gain = 2.4v v gain = 1.5v figure 5. rx mixer conversion gain vs. rf frequency, t a = +25 c, v pos = 3 v, v gref = 1.2 v, f if = 26 mhz if frequency ?mhz 20 15 10 14 18 26 34 42 10 5 0 gain ?db ? 22 30 38 46 50 v gain = 1.5v v gain = 0.2v v gain = 2.4v figure 6. mixer conversion gain vs. if frequency, t a = +25 c, v pos = 3 v, v gref = 1.2 v, f rf = 250 mhz temperature ? c 70 50 ?0 ?0 ?0 0 20 40 40 30 20 gain ?db 10 ?0 10 30 50 60 amp/demod, v pos = 2.7v to 3.6v mixer, v pos = 2.7v to 3.6v 70 80 90 60 figure 7. rx mixer conversion gain and if amplifier/ demodulator gain vs. temperature, v gain = 0.2 v, v gref = 1.2 v, f if = 26 mhz, f rf = 250 mhz v gain ?volts ?2 0 ?3 ?4 ?5 ?6 v pos = 2.7v, t a = +85 c ?0 v pos = 2.7v, t a = +25 c v pos = 2.7v, t a = ?5 c v pos = 3.6v, t a = ?0 c v pos = 3.6v, t a = +85 c 0.5 1.0 1.5 2.0 2.5 ?1 input ?dbm (referred to 50 w ) figure 8. rx mixer input 1 db compression point vs. v gain , v gref = 1.2 v, f rf = 250 mhz, f if = 26 mhz
AD6432 C8C rev. 0 intermediate frequency ?mhz 30 10 20 10 0 if amp/demod gain ?db ?0 50 v gain = 0.2v 15 20 25 30 35 40 60 70 40 45 v gain = 0.5v v gain = 1.5v v gain = 2.4v figure 9. if amplifier and demodulator gain vs. if frequency, t a = +25 c, v pos = 3 v, v gref = 1.2 v if input frequency ?mhz 10 15 20 25 30 35 13000 40 45 50 12000 11000 10000 9000 8000 7000 6000 5000 4000 3000 r s v gain = 2.4v r s v gain = 1.2v r s v gain = 0.2v c s v gain = 0.2v c s v gain = 1.2v c s v gain = 2.4v capacitance ?pf 2.0 resistance ? w 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 figure 10. if amplifier input impedance vs. frequency, t a = +25 c, v pos = 3 v, v gref = 1.2 v v gain ?volts 0 0.5 1.0 1.5 2.0 2.5 ?0 ?0 ?0 ?0 ?0 ?0 0 if input 1db compression referred to 50 ohms ?dbm figure 11. if amplifier/demodulator input 1 db compression point vs. v gain , f if = 26 mhz, v gref = 1.2 v, t a = +25 c, v pos = 3 v v gain ?volts 0 0.5 1.0 1.5 2.0 2.5 ?.2 ?.1 0 0.1 0.2 0.3 0.4 gain error ?db mixer if amp/demod figure 12. gain error vs. gain control voltage, t a = +25 c, v pos = 3 v, v gref = 1.2 v, f rf = 250 mhz, f if = 26 mhz demodulator vco frequency ?mhz 10 15 20 25 30 35 ?.4 ?.2 ?.0 ?.8 ?.6 ?.4 40 45 ?.2 0 0.2 0.4 0.6 demodulator quadrature error ?degrees figure 13. demodulator quadrature error vs. fref frequency, t a = +25 c, v pos = 3 v frequency offset ?khz 0.1 1.0 10 100 1000 ?10 ?05 ?0 ?5 ?0 ?5 ?00 phase noise ?dbc/hz if = 26mhz if = 13mhz figure 14. pll phase noise vs. frequency, v pos = 3 v, c fltr =1 nf, r fltr =1 k w , fref = 13 mhz
AD6432 C9C rev. 0 frequency of vco ?mhz 10 40 50 ?.2 ?.0 0 ?.2 ?.4 ?.6 ?.8 filter pin voltage referenced to v pos ?volts 15 20 25 30 35 45 ?.4 t a = ?0 c t a = +25 c t a = +85 c figure 15. pll loop voltage at fltr pin (kvco) vs. frequency gain voltage ?volts 0 ?0 ?0 ?0 ?0 ?0 ?0 0.5 1.0 1.5 2.0 2.5 ?0 input 1db compression point referred to 50 ohms ?dbm figure 16. s ystem (mixer + if lc filter + if amplifier + demodulator) 1 db compression point vs. v gain , t a = +25 c, v pos = 3 v, f rf = 250 mhz, f if = 26 mhz, v gref = 1.2 v gain voltage ?volts 0 ?0 ?0 ?0 ?0 ?0 ?0 0.5 1.0 1.5 2.0 2.5 ?0 0 system input ip3 referred to 50 ohms ?dbm figure 17. system (mixer + if lc filter + if amplifier + demodulator) ip3 vs. v gain , t a = +25 c, v pos = 3 v, f if = 26 mhz, f rf = 250 mhz, v gref = 1.2 v v gain ?volts 0 4 6 14 12 10 8 0.5 1.0 1.5 2.0 2.5 2 16 conversion gain ?db 0 ? ? figure 18. rx mixer conversion gain vs v gain , t a = +25 c, v pos = 3 v, f rf = 250 mhz, f if = 26 mhz, v gref = 1.2 v v gain ?volts 0 40 50 70 60 0.5 1.0 1.5 2.0 2.5 30 20 if amp/demodulator gain ?db 10 0 figure 19. if amplifier/demodulator gain vs. v gain , t a = +25 c, v pos = 3 v, f rf = 250 mhz, f if = 26 mhz, v gref = 1.2 v gain voltage ?volts 0 40 50 70 60 0.5 1.0 1.5 2.0 2.5 30 20 10 0 80 system gain ?db figure 20. system (mixer + if lc filter + if amplifier + demodulator) gain vs. v gain , t a = +25 c, v pos = 3 v, f if =26 mhz, f rf = 250 mhz, v gref = 1.2 v
AD6432 C10C rev. 0 temperature ? c ?0 ?8.0 ?7.5 ?6.5 ?7.0 ?0 0 20 40 60 ?8.5 ?9.0 ?9.5 ?0.0 ?6.0 transmit desired sideband gain ?db 80 100 figure 21. tx desired sideband gain vs. temperature, t a = +25 c, v pos = 3 v, f carrier = 280 mhz, i and q inputs driven in quadrature carrier frequency ?mhz 100 ?5.5 ?5.0 ?4.0 ?4.5 120 140 160 180 200 ?6.0 ?6.5 ?7.0 ?7.5 ?3.5 transmit desired sideband gain ?db 220 240 ?8.0 ?8.5 ?9.0 260 280 300 figure 22. tx desired sideband gain vs. f carrier , t a = +25 c, v pos = 3 v temperature ? c ?0 ?7.0 ?6.5 ?5.5 ?6.0 ?0 0 20 40 60 ?7.5 ?8.0 ?8.5 ?9.0 ?5.0 80 100 ?9.5 ?0.0 typical undesired sideband suppression ?dbc figure 23. tx typical undesired sideband suppression vs. temperature, t a = +25 c, v pos = 3 v carrier frequency ?mhz 100 ?7.0 ?6.5 ?5.5 ?6.0 120 140 160 180 200 ?7.5 ?8.0 ?8.5 ?9.0 ?5.0 240 260 ?9.5 ?0.0 280 300 220 typical undesired sideband suppression ?dbc figure 24. tx typical undesired sideband suppression vs. f carrier , t a = +25 c, v pos = 3 v gain voltage ?volts 0 10 supply current ?ma 12 14 16 18 20 22 0.5 1.0 1.5 2.0 2.5 v pos = 3.6v, t a = +85 c v pos = 2.7v, t a = +85 c v pos = 3.6v, t a = +25 c v pos = 3v, t a = +25 c v pos = 2.7v, t a = +25 c v pos = 3.6v t a = ?0 c v pos = 2.7v t a = ?0 c figure 25. rx mode supply current vs. v gain , v gref = 1.2 v temperature ? c ?0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 ?0 0 20 40 60 v pos = 3.6v v pos = 3v v pos = 2.7v tx mode supply current ?ma 80 100 14.0 14.5 15.0 figure 26. tx mode supply current vs. temperature
AD6432 C11C rev. 0 product overview the AD6432 provides most of the active circuitry required to realize a complete low power, single-conversion superhetero- dyne time division transceiver, or the latter part of a double- conversion transceiver, at input receive frequencies up to 350 mhz with an if from 10 mhz to 50 mhz and transmit frequencies up to 300 mhz. the internal i/q demodulators, with their associated phase-locked loop and the internal i/q modulator, support a wide variety of modulation modes, includ- ing n-psk, n-qam, and gmsk. a single positive supply volt- age of 3 v is required (2.7 v minimum, 3.6 v maximum) at a typical supply current of 13 ma at midgain in receive mode and 13 ma in transmit mode. in the following discussion, v pos will be used to denote the power supply voltage, which will be as- sumed to be 3 v. 31 19 21 23 24 25 26 16 6 9 10 13 14 17 rfhi rflo mxop mxom lc bandpass filter ifip ifim 90 0 3mhz 4.7k w 4.7k w 4.7k w 4.7k w divide by 1 or 2 phase detector gain temp. compensation 33 29 20 39 42 43 40 41 38 37 lohi lolo modo pcao 5 2 35 90 0 irxn irxp qrxn qrxp ifs0 fref fltr gain gref rxpu txpu itxn itxp qtxn qtxp pcap pcam quadrature vco rx, tx bias 2 AD6432 figure 27. functional block diagram figure 27 shows the main sections of the AD6432. in the re- ceive path, it consists of a variable-gain uhf mixer and linear two-stage if strip, both of which together provide a calibrated voltage-controlled gain range of more than 80 db, followed by a tunable if bandpass filter and dual quadrature demodulators. these are driven by inphase and quadrature clocks generated by a phase-locked loop (pll) locked to a corrected external reference. in the transmit path it consists of a quadrature modu- lator followed by a low-pass filter. the quadrature modulator is driven by quadrature frequencies that are generated internally by dividing the external local oscillator frequency by two. a cmos-compatible power-down interface completes the AD6432.
AD6432 C12C rev. 0 receive mixer the uhf mixer is an improved gilbert-cell design that can operate from low frequencies (it is internally dc-coupled) up to an rf input of 350 mhz. the dynamic range at the input of the mixer is determined, at the upper end, by the maximum input signal level of 71 mv (C13 dbm in 50 w between rfhi and rflo) up to which the mixer remains linear and, at the lower end, by the noise level. it is customary to define the linearity of a mixer in terms of the 1 db gain-compression point and third- order inter cept, which for the AD6432 are C13 dbm and 0 dbm, respectively, in a 50 w system. the mixers rf input port is differential, that is, pin rflo is functionally identical to rfhi, and these nodes are internally biased. the rf port can be modeled as a parallel rc circuit as shown in figure 29. the local oscillator input of the receive mixer is internally provided by the lo divided by two. rfhi rflo c sh r sh figure 28. mixer port modeled as a parallel rc network at v gain = 1.2 v and f rf = 250 mhz, c sh = 3.5 pf and r sh = 400 w (see figure 4) the output of the mixer is differential. the nominal conversion gain is specified for operation into a 26 mhz lc if bandpass filter, as shown in figure 29 and table i. mxop c1 c2 c1 l1 mxom ifim ifip figure 29. suggested if filter inserted between the mixers output port and the amplifiers input port the conversion gain is measured between the mixer input and the input of this filter, and varies between C3 db and +15 db. table i. filter component values for selected frequencies frequency c1 l1 c2 13 mhz 27 pf 0.82 m h 180 pf 26 mhz 22 pf 0.39 m h 82 pf the maximum permissible signal level between mxop and mxom is determined by the maximum gain control voltage. the mixer output port, having pull-up resistors of 250 w to vprx, is shown in figure 30. vprx mxop 250 w 250 w mxom figure 30. mixer output port if amplifier most of the gain in the AD6432 receive section is provided by the if amplifier strip, which comprises two stages. both are fully differential and each has a gain span of 31 db for the agc volt- age range of 0.2 v to 2.4 v. thus, in conjunction with the v ari- able gain of the mixer, the total gain span is 80 db. the overall if gain varies from C14 db to +48 db for the nominal agc voltage of 0.2 v to 2.4 v. maximum gain is at v gain = 0.2 v. the if input is differential, at ifhi and iflo. figure 32 shows a simp lified schematic of the if interface mod eled as parallel rc network. the operat ive range of the if amplifier is approxi mately 50 mhz from ifhi and iflo through the demodulator. ifhi iflo c sh r sh figure 31. if amplifier port modeled as a parallel rc network for v gain = 1.2 v and f if = 26 mhz, c sh = 3 pf, r sh = 8.5 k w (see figure 10) gain scaling the overall gain of the AD6432, expressed in decibels, is linear with respect to the agc voltage v gain at pin gain. the gain of all sections is maximum when v gain is 0.2, and falls off as the bias is increased to v gain = 2.4 v and is independent of the power supply voltage. the gain of all stages changes simulta- neously. the AD6432s gain scaling is also temperature- compensated. note that gain pin of the AD6432 is an input driven by an external low impedance voltage source, normally a dac, under the control of radios digital processor. the gain-control scaling is directly proportional to the reference voltage applied to the pin gref and is independent of the power supply voltage. when this in put is set to the nominal value of 1.2 v, the scale is nominally 27.5 mv/db (36.4 db/v). under these conditions, 80 db of gain range (mixer plus if) corresponds to a control voltage of 0.2 v < = v g < = 2.4 v. the final centering of this 2.2 v range depends on the insertion losses of the if filters used. pin gref can be tied to an external voltage reference, v ref , provided, for example, by a ad1580 (1.21 v) voltage reference. when using the analog devices ad7013 (is54, tetra and satellite receiver applications) and ad7015 or ad6421 (gsm, dcs1800, pcs1900) baseband converters, the external refer- ence may also be provided by the reference output of the
AD6432 C13C rev. 0 baseband converters. the interface between the AD6432 and the ad6421 baseband converter is shown in figure 35. the ad7015 baseband converter provides a v r of 1.23 v; an auxil- iary dac in the ad7015 can be used to generate the agc voltage. since it uses the same reference voltage, the numerical input to this dac provides an accurate rssi value in digital form, no longer requiring the reference voltage to have high absolute accuracy. tunable filter and i/q demodulators the demodulators (i and q) receive their inputs internally from the if amplifier through a two-pole tunable-frequency bandpass filter. this filter is centered on the if frequency and its band- width is approximately equal to forty per cent of the if fre- quency. the filter attenuates the amount of noise present at the input of the demodulators. each demodulator comprises a full-wave synchronous detector followed by a 3 mhz, two-pole low-pass filter, producing differ- ential outputs at pins irxp and irxn, and qrxp and qrxn. using the i and q demodulators for ifs above 50 mhz is pre- cluded by the 10 mhz to 50 mhz range of the pll used in the demodulator section. the i and q outputs are differential and can s wing up to 2 v p-p at the low supply voltage of 2.7 v. they are nominally centered at 1.5 v independent of power supply. they can therefore directly drive the receive adcs in the ad7015 or ad6421 baseband converters, which require an amplitude of 1.23 v to fully load them when driven by a differential signal. the conver- sion gain of the i and q demodulators is 17 db. a simple 1-pole rc filter at the i and q outputs, with its corner above the modulation bandwidth is sufficient to attenuate un- desired outputs. the design of the rc filter is eased by the 4.7 k w resistor integrated into each i and q output pin. phase-locked loop the demo dulators are driven by quadrature signals that are provided by a variable-frequency quadrature oscillator (vfqo), phase-locked to the reference frequency. this frequency is equal or double the frequency of the signal applied to pin fref. when the quadrature signals are at the if, inphase and quadra- ture baseband outputs are generated at the i output (irxp and irxn) and q output (qrxp and qrxn), respectively. the quadrature accuracy of the vfqo is typically within 1 at 26 mhz. a simplified diagram of the fref input is shown in figure 32. vpos 5k w 20k w 5k w fref 50 a ptat figure 32. simplified schematic of the fref interface the vfqo is controlled by the voltage between v pos and fltr. in normal operation, a series rc network, forming the pll loop filter, is connected from fltr to v pos . the use of an integral sample-hold system ensures that the frequency- control voltage on pin fltr remains held during power- down, so reacquisition of the carrier occurs in less than 80 m s. in practice, the probability of a phase mismatch at power- up is high, so the worst-case linear settling period to full lock needs to be considered in making filter choices. this is typically < 80 m s for a locking error of 3 at an if of 26 mhz. note that the vfqo always provides quadrature between its own i and q outputs, but the phasing between it and the reference carrier will swing around the final value during the plls settling time. i and q transmit modulator the transmit modulator uses two standard mixer cells whose linear inputs are the differential voltages at the input pins itxp/itxn and qtxp/qtxn, respectively and whose local oscillator inputs are derived from a divide-by-two cell, driven from the input applied to pins lohi/lolo. the outputs of the mixers are summed and converted to single- sided form. the output stage also f ilters the higher harmon- ics, minimizing the need for filtering before this signal is presented to the up-converter in a typical transmitter configuration. the i and q inputs are intended to be driven using a fully-differential drive (for example from an ad7015 or ad6421) and need to be biased to a common-mode dc level of 1.2 v, with a typical differential amplitude of 1.028 v (that is, 514 mv at each input). some small variation in the drive conditions is allowable, but will result in nonoptimal performance. the minimum instantaneous input should not go below 0.6 v and the maximum voltage should not exceed 1.8 v using a 2.7 v supply (in general, vp C 0.9 v). the impedance at these inputs is several m w in parallel with approximately 1 pf; the bias currents flow out of the pins and are ~100 na. these conditions permit the use of a high impedance low-pass filter if desired ahead of the modulator inputs. the dc modulator output is at a constant dc level of 1.5 v, independent of temperature and supply voltage. it is de- signed to drive a 150 w load and should either be matched into a 50 w load, using a simple lc network, or padded to 150 w with a series 100 w resistor (figure 33). the output is short-circuit-proof. the output modulated signal at pin modo has a power of C16 dbm when driving a 50 w load with a 100 w series resistor, as shown in figure 33. this power is specified at a carrier frequency of 272 mhz with a maximum dc differential signal applied to the i or q chan- nel while the other channel has no differential signal ap- plied. the transmit modulator is enabled only when the txpu input (pin 39) is taken hi. 50 w 100 w modo 100pf figure 33. output impedance of pin modo is designed to drive a 50 w load with a 100 w series resistor
AD6432 C14C rev. 0 local oscillator input the local oscillator (lo) input port is differential and consists of two functionally identical pins, lohi and lolo. it accepts a signal of 200 mv p-p at a frequency between 200 mhz and 600 mhz. inputs lohi and lolo are internally biased to the positive supply (pin 3) through 500 w resistors. while not usu- ally needed, these inputs may be driven through a simple match- ing network to lower the lo power required from a 50 w source. single-sided drives are not recommended. the most noticeable effects will be degradation of phase balance and an increase in phase noise. this signal is fed internally to a divider by two that generates the mixing signals for the receive mixer and the transmit modulator. in order to meet the phase and amplitude balance of the trans- mit quadrature modulator, as stated in the specification table, the duty cycle of the lo signal must be such that the second harmonic is at least 30 dbc below the fundamental. i/q convention the AD6432 is a complete if subsystem. although not a re- quirement for using the AD6432, most applications will use a high side lo injection on the receive mixer. the i and q con- vention on the receive section is such that when a spectrum with i leading q is presented to the input of the receive mixer and a high side lo is presented to the receive mixer, i still leads q at the baseband output of the AD6432. likewise, the i and q convention on the transmit section is such that when a spectrum with i leading q is presented at the baseband input of the modulator, i still leads q at the output of the modulator. auxiliary op amp an auxiliary operational amplifier is available although it is im- portant to remember that it is active only when txpu is high. the positive and negative input terminals are pcap and pcam with pcao being the output pin. the inputs are the bases of pnp transistors with a typical bias current of approximately 150 na. the input offset voltage is typically < 4 mv and the open loop gain of the amplifier is 60 db. the amplifier is unity gain stable with a C3 db bandwidth greater than 40 mhz. the input signal voltage range is from 0.1 v to v pos C 2.1 v. bias system the AD6432 operates from a single supply, v pos , usually 3 v, at a typical supply current in receive mode of 13 ma at midgain and t a = +25 c, corresponding to a power consumption of 39 mw. any voltage from 2.7 v to 3.6 v may be used. the bias system includes a fast-acting active high cmos-com- patible power-up switch, allowing the part to idle at less than 100 m a when disabled. biasing is generally proportional-to- absolute temperature (ptat) to ensure stable gain with tem- perature. other special biasing techniques are used to ensure very accurate gain, stable over the full temperature range. using the AD6432 in this section, we will focus on a few areas of special impor- tance through the real life example of interfacing the AD6432 to the ad6421 base band converter. as is true of any wideband high gain components, great care is needed in pc board layout. the location of the particular grounding points must be considered with due regard for the possibility of unwanted signal coupling. the high sensitivity of the AD6432 leads to the possibility that unwanted local em signals may have an effect on the per- formance. during system development, carefully-shielded test assemblies should be used. the best solution is to use a fully enclosed box enclosing all components, with the minimum number of needed signal connectors (rf, lo, i and q outputs) in miniature coax form. interfacing the AD6432 to the ad6421 baseband converter the ad6421 baseband converter contains all the necessary elements to drive the AD6432. receive interface the interface between the two devices provides for quadrature i and q channels that can be driven either differentially or in the single-ended configuration. figure 35 shows the interface be- tween the AD6432 and the ad6421 for the differential configu- ration. the respective pins (irxp, irxn, qrxp and qrxn) are dc coupled through 4.7 k w resistors, which are integrated within the AD6432. balanced coupling may be used with a single 50 pf capacitor between the complementary signals as illustrated in figure 35. this low-pass filter is the only external filter required to prevent aliasing of the baseband analog signal prior to sampling within the ad6421. the ad6421 has an external autocalibration mode that can calibrate out any offsets resulting from the if demodulation circuitry. transmit interface the corresponding transmit (itxp, itxn, qtxp and qtxn) pins of the ad6421 and AD6432 are directly connected as these have compatible bias levels for dc coupling. to meet the more stringent phase two filter mask requirements, an external low- pass filter may be required, depending on the filtering capabili- ties of the radio section. a passive second order low-pass filter network with a cutoff frequency to 600 khz is suggested as shown in figure 34. resistor values should range from 1.5 k w C3.0 k w to minimize AD6432 offsets. qtxn qtxp itxn itxp AD6432 ad6421 itxp itxn qtxp qtxn figure 34. gsm phase ii transmit interface
AD6432 C15C rev. 0 gain control the AD6432 contains a gain tc compensation circuit that provides a nominal 80 db dynamic range of automatic gain control. the gain input pin of the gain circuit is driven by the ad6421 automatic gain control dac (agcdac), an integrated auxiliary dac of the ad6421, controllable by the radios digital processor. this connection should be made through a single pole rc to reduce high frequency noise into the gain control circuit. the values shown in figure 35 provide a C3 db point at approximately 1 mhz, sufficient for the gain control. gain control scaling is directly proportional to the reference voltage applied to pin gref and is independent of the power supply voltage. a nominal 1.2 v reference for gref can be provided by the ad6421 through brefout. brefout is a buffered output version of brefcap reference. this refer- ence output feature is enabled on the ad6421 by setting bit 2 in control register bcrb (bcrb2). see ad6421 data sheet. the v gain input range for this control signal is 0.2 vC 2.4 v where gain is maximum at 0.2 v and falls off as v gain is increased to 2.4 v. to avoid saturating the input to the baseband converter, the automatic gain control function of the r eceiver must limit the output signal swing of the AD6432 to 1.2 v, the full signal range of the input. phase-lock loop control the AD6432 pll/qvco circuits require an external frequency reference for coherent modulation and demodulation of the baseband and if signal. the external frequency reference con- trol for the AD6432 pll/qvcos is typically generated through a 13 mhz voltage controlled temperature compensated crystal oscillator (vctcxo). the control voltage for the vctcxo is generated by an auxiliary dac in the ad6421 designated as the automatic frequency control dac (afcdac). the pll loop is closed through the radios algorithm signal processor, which drives the ad6421 afcdac. the AD6432 fref pin provides the vctcxo reference sig- nal to the AD6432 rx quadrature vco (qvco) circuit. the AD6432 fref input must be an ac coupled signal 200 mv p-p or greater. the reference for the uhf tx qvco and rx if down converter is synthesized from the vctcxo output reference signal through an external frequency synthe- sizer and vco. this uhf reference is an ac coupled input into AD6432 lohi and lolo pins. an external series rc network connected between fltr (pin 29) and the vpos supply pin provides the proper loop filter for the vco/pll as shown in figure 35. lc band- pass filter frequency synthesizer vctcxo 50pf 1k w 100nf 0.1 f 160 w 1nf 1nf itxp itxn qtxp qtxn ad6421 irxp irxn qrxp qrxn afcdac mclk brefcap brefout agcdac ramdac power control 50pf gain gref lolo lohi fref qrxn qrxp irxn irxp qtxn qtxp itxn itxp ifhi iflo mxlo mxhi AD6432 figure 35. AD6432 to ad6421 interface transmit power control a general purpose amplifier is available on the AD6432, which may be useful as part of an automatic control circuit for the power amplifier. open ended, this amplifier will swing full scale from rail to rail. it is recommended that this amplifier be con- nected in the unity feedback configuration when not being used by connecting pcao to pcam. AD6432 evaluation board the AD6432 evaluation board is designed to enable measure- ments of key parameters on the AD6432 ific, a device that provides the complete transmit and receive if signal processing, including i/q modulation and demodulation, necessary to imple- ment a digital wireless transceiver. many of the signal paths into and out of the AD6432 are differ- ential, which is the preferred interface to and from single supply codecs. to facilitate an interface to traditional lab equip- ment, the following interface circuitry is included on the board. a 20-pin berg strip for bias, gain and inphase and quadrature signal interface. end launch sma connectors for rf, lo, modo and fref signals and provisions for breaking out mxop and ifhi with rf transformers. a single-ended to differential rf transformer provides a bal- anced lo drive. an onboard 1.2 v dc reference ic is provided for application to gref.
AD6432 C16C rev. 0 evaluation board description this four layer board demonstrates both the transmit and receive functions of the AD6432. the top internal layer is a ground plane and the bottom internal layer is a strategically partitioned power plane with dut power and bipolar support device power. a 20-pin berg strip connector provides the external power and dc signal interface, which includes power-up, gain and external reference bias options. the various high frequency if, lo, tx modulation output (modo) and the demodulator reference (fref) are brought in and out of the board via end-launch sma connectors. appropriate terminations are provided for each signal. several hardware jumpers are provided for bias and if selection options. figure 36 shows the placement of the different connectors used on the evaluation board. fref modo loinp optlo rfhi t1 u1 q1 j23 j25 j24 j26 j21 interface connector 1 AD6432 eval. rev. b mxop ifip j22 figure 36. evaluation board layout (top view) note: mxop, ifhi, optlo are optional sma connectors not supplied with the evaluation board. interface connector (berg strip) pin description building up a simple idc connector/ribbon cable breakout to a vector board or box with banana plugs will facilitate testing. figure 37 shows the signals placement and table ii describes each signal. board edge gnd itxp itxn qtxp pcam pcap vs2 vs1 pcao ifs0 irxp irxn qrxp qrxn gref gain qtxn txpu rxpu gnd figure 37. evaluation board interface connector
AD6432 C17C rev. 0 table ii. connector signal description pin name description gnd analog and power ground. itxp i channel transmit plus modulation input. itxn i channel transmit minus modulation input. qtxp q channel transmit plus modulation input. qtxn q channel transmit minus input. txpu transmit section power-up. this function is also jumper selectable with j21. pcam auxiliary op amp minus input. pcap auxiliary op amp plus input. vs2 power control op amp supply 2.7 v dcC3.6 v dc. the jumper, j26, connects vs1 and vs2 together. vs1 AD6432 main supply 2.7 v dcC3.6 v dc. pcao auxiliary op amp output. ifs0 selects if pin. this function is also jumper pro- grammable with j25. irxp i channel receive plus modulation output. irxn i channel receive minus modulation output. qrxp q channel receive plus modulation output. qrxn q channel receive plus modulation output. gref the AD6432 gain reference bias which is optimized for 1.2 v dc. this may be externally supplied; or by shorting j23, supplied directly from the ad1580 sot-23 onboard, 1.2 v reference. gain max rx gain occurs at 0.2 v dc. minimum gain occurs at 2.4 v dc. rxpu receive section power-up. this function is also jumper selectable with j22. power requirements the evaluation board uses two supplies, vs1 and vs2. vs12.7 v dcC3.6 v dc, 13 ma typical. this is the main sup- ply for the AD6432. vs22.7 v dcC3.6 v dc, 2 ma typical. this is the supply for the on-chip op amp which is normally used in rf power control circuits. the op amp is active only in the transmit mode. table iii. sma end-launch connectors sma connector description modo transmit modulator output. this pin, which is designed to drive a 150 w filter, has been resistively matched (loss) onboard to drive a 50 w instrument such as a spectrum analyzer. loip local oscillator input pin. this is actually fed with twice the lo frequency from a generator for both transmit and receive. the nominal lo level is C16 dbm (50 w ). optlo optional differential minus local oscillator input (transformer can be removed). rfhi rf input mxop mixer output (optional output that may be converted to single ended output with an rf transformer). ifhi if input (optional single ended input that may be converted to differential with an rf transformer). fref frequency reference for phase locked receive de- modulator. the internal vco frequency is equal to fref in the 1x mode and equal to two times fref in the 2x mode.
AD6432 C18C rev. 0 4 6 123 4 6 123 mxop r6 open c18 open l1 open l2 short l3 short c16 22pf c19 22pf c20 82pf l4 0.39 h r13 open t2 c42 0.01 f r3 49.9 w c1 100pf r9 84 w modo r25 1k w c29 0.1 f r34 0 w c11 0.01 f c10 1nf c32 0.1 f vs2 vpdv decoupling vs1 r2 0 w r23 123 w qtxn qtxp itxn pcap r30 1k w c5 0.01 f r12 0 w r1 1k w r14 125 w r8 0 w ifs1 ifs0 c36 1nf r6 0 w c41 0.01 f c17 0.1 f c23 0.01 f r7 0 w c6 47pf c8 47pf irxp irxn qrxp qxrn c28 0.1 f vptx decoupling c14 0.01 f c15 100pf loip itxp vs1 rfhi c2 100pf r31 0 w vs1 c30 0.1 f c3 0.01 f rxpu gain gref pcao fref vs1 c21 0.1 f j22 vs1 c44 0.01 f tp1580 r16 10k w q1 j23 vs1 r35 125 w optlo r20 open txpu pcam r39 open vs1 r19 20k w j21 vs1 j26 r17 20k w r18 20k w itxp itxn qtxp qtxp txpu pcam pcap pcao ifs0 gnd irxp irxn qrxp qrxn gref gain rxpu gnd c50 4.7 f c12 4.7 f tx 20a 20b vs2 vs1 j24 j25 29 30 31 32 33 27 28 25 26 23 24 40 39 38 41 42 43 44 36 35 34 37 12 13 14 15 16 17 18 19 20 21 22 3 4 5 6 7 1 2 10 11 8 9 vpdv modo gnd cmtx lolo lohi cmrx gnd rflo rfhi gnd fref gnd ifs0 cmdm fltr vpfl vpdm irxp irxn qrxp qrxn vptx itxp itxn qtxp qtxn txpu pcap pcam gnd vprx mxhi mxlo iflo ifhi vppc cmif cmif rxpu gain gref gnd AD6432 top view (pins down) pcao r21 0 w c18 0.1 f 1 2 3 4 6 t1 r15 20k w ifip t3 c43 0.01 f figure 38. evaluation board schematics
AD6432 C19C rev. 0 outline dimensions dimensions shown in inches and (mm). 44-lead plastic thin quad flatpack (tqfp) (st-44) top view (pins down) 1 33 34 44 11 12 23 22 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) bsc 0.394 (10.0) sq 0.472 (12.00) sq 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) seating plane 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45)
C20C c3061C12C4/97 printed in u.s.a.

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